1. Field of the Invention
The present invention relates to a semiconductor nonvolatile memory and, more particularly, improvement in integration, speed of operation and productivity thereof.
2. Description of the Prior Art
In related art, there is an instance of semiconductor nonvolatile memory 1 as shown in FIG. 1. Referring to FIG. 1, a P type well 2 includes a drain 3 and a source 4, the two region forming a space comprising a region 10a and a region 10b. Between the region 10a and a memory gate electrode 5 is an insulating layer 6 for holding electrons. This insulating layer 6 has a structure of three layer: a silicon dioxide layer 6a, a silicon nitride layer 6b, and a silicon dioxide layer 6c. The silicon nitride layer 6b is where electrons can be trapped by bias between the well 2 and the memory gate electrode 5. The insulating layer 6 and a silicon dioxide layer 8 insulate a control gate electrode 7 from both the memory gate electrode 5 and the region 10b.
It is arranged that the region 10b changes from nonconductive into conductive when a stable positive voltage is applied to the control gate electrode 7 and that the region 10a changes from conductive into nonconductive when a stable positive voltage is applied to the gate electrode 5.
The operations of writing data into and reading data from the nonvolatile memory 1 will be described. To write data into the memory 1, a positive voltage such as 9 V is applied to the memory gate electrode 5 relative to the drain 3 and the source 4, whereby electrons in the P type well 2 move into the insulating layer 6 and get trapped therein. This change in charge distribution due to the trapped electrons cause the region 10a to change from conductive into nonconductive. These electrons remain trapped in the insulating layer 6 even when the voltage applied to the memory gate electrode 5 is cut off. This state wherein electrons are trapped in the insulating layer 6 is referred to as "write state" hereinafter.
In the reading operation, a positive voltage, which is larger than the threshold voltage for the conductive channel of the region 10b, is applied to the control gate electrode 7 relative to the drain 3 and the source 4, whereby the region 10b changes from nonconductive into conductive.
Therefore, when the insulating layer 6 has electrons trapped therein and a voltage is applied to the drain 3 relative to the source 4 a current flows between the drain 3 and the source 4. It is because the regions 10a and 10b are conductive. Conversely, when the insulating layer 6 have no electron trapped therein and a voltage is applied to the drain 3 relative to the source 4, no current flows between the drain 3 and the source 4. This is because the region 10a is nonconductive.
As is described above, it can be determined whether or not the memory 1 is in "write state", by determining whether or not a current flows between the drain 3 and the source 4.
To erase data from the nonvolatile memory, a positive voltage is applied to the P type well 2 relative to the memory gate electrode 5. This application of the voltage causes the electrons trapped in the insulating layer 6 to return the well 2. This indicates that the data of the memory has been erased.
A memory circuit can be constructed by using the above-mentioned memories 1 which array in rows and columns. The memory circuit is shown in partial view of equivalent circuit 15 in FIG. 2A. As shown in FIG. 2A, each word line W connects with all control gate electrodes of memories arrayed in a row and each word line X connects with all memory gate electrodes of memories arrayed in a row and each bit line connects with all drains of memories arrayed in a column and a well line PW connects with sources of all of the memories arrayed in rows and columns as well as wells for each of them.
So as not to write data into and read data from memories other than a desired memory, the following means can select a desired memory from the memory circuit.
FIG. 2B is a table showing an example of combinations of voltages applied to each of the individual lines at writing, erasing and reading operations, the combination enabling the memory circuit to select a desired memory, for example, a memory C11 at writing and reading operations.
More specifically, to write data into the selected memory C11, a voltage of 5 V is applied to both the word line W1 and the bit line B2 and a voltage of -4 V is applied to each of the other individual lines. That means that a positive voltage of 9 V (volts) is applied to the memory gate electrode 5 of the selected memory C11 relative to the well 2, the source 4 and the drain 3. As a result of the application, the insulating layer 6 of the selected memory C11 traps electrons therein.
Referring to the nonselected memory C12, the voltage of 5 V is applied to the memory gate electrode 5 and thereby the region 10a changes into conductive. The voltage of 5 V applied to the drain 3 can travel into the region 10a. That is, there is no potential difference between the memory gate electrode 5 and the well 2. Therefore, the insulating layer 6 of the nonselected memory C12 traps no electrons therein. Referring to the other nonselected memories C13 and C14, the voltage of -4 V is applied to the memory gate electrode 5. Therefore, the insulating layer 6 traps no electrons therein, respectively.
Note that the voltage of -4 V is applied to the word lines X1 and X2 in order that all the regions 10b of memories C11, C12, C13 and C14 get nonconductive. Therefore, the voltage of 5 V applied to the bit line B2 can travel into the region 10a of the memory C12 without a loss.
Reading operation is effected by applying a voltage of 5 V to a word line X1, applying a positive voltage to the bit line B1 connected to a sense amplifier, leaving the bit line B2 floating and applying a voltage of 0 V to each of the other individual lines.
Referring to the selected memory C11, the region 10b is conductive because the voltage of 5 V is applied to the control gate electrode 7. When the memory C11 has electrons trapped in the insulating layer 6 the region 10a is nonconductive. Therefore, no current flows through the bit line B1. Conversely, when the memory C11 has no electrons trapped in the insulating layer 6 the region 10a is conductive. Therefore, a current flows through the bit line B1.
Referring to the nonselected memory C12, the region 10b is conductive because the voltage of 5 V is applied to the control gate electrode 7. However, since the source 4 is in a voltage of 0 V applied and the bit line B2 is left floating, no current flows through the a bit line B2 even when the region 10a is conductive. Referring to the other nonselected memories C13 and C14, the region 10b is nonconductive respectively because the word line X2 is at a voltage of 0 V applied. Therefore, no current flows through the bit line B1 and through the bit line B2 respectively.
As is described above, in the memory circuit, data can be written into and read from a desired memory.
Meanwhile, erasing operation is effected by applying a voltage of -4 V to all of the word line X1, the word line X2 and the word line W1, and applying a voltage of 5 V to the other individual lines.
Referring to the selected memory C11 and C12, since the well line PW has a voltage of 5 V and the memory gate electrode 5 has a voltage of -4 V, the electric field developed between the well 2 and the memory gate electrode 5 causes electrons in the insulating layer 6 move into the well 2. This indicates that the data of the memories C11 and C12 has been erased.
Referring to the nonselected memories C13 and C14, since the well 2 has a voltage of 5 V and the memory gate electrode 5 has a voltage of 5 V, no electric field develops between the well 2 and the memory gate electrode 5. Therefore, the data of the memories C13 and C14 is left unchanged.
The above-mentioned memory circuit, however, has a flowing problem.
Each of the memories in the memory circuit comprises two field effect transistors with a common source and a common drain.
These two field effect transistors bar the memory cell and the memory circuit from integrating and being manufactured easily.
Meanwhile, in order to control the conductivity of the region 10b by application of electric field between the well 2 and the control gate electrode 7, it is necessary to arrange a certain width of the region 10b correctly during the manufacturing process. This width W is determined by a width of a photoresist pattern using as a mask. In lithography technique, it is difficult to locate the photoresist pattern mask at a predetermined position in the substrate. Therefore, it is difficult to form the region 10b with a predetermined width.